Inference Chips for Agent Workflows
Purpose-built silicon for the agent execution loop — and the compiler that makes the chip work.
Championed by Diana Hu at YC
THE PROBLEM
What needs to be solved
AI agents don't use hardware the way LLM chatbots do. An agent's workload is a continuous loop: observe → reason → act → observe again, with variable-length contexts, tool calls, memory reads, and branching logic. GPUs are optimized for batch matrix multiplication — great for training, but wasteful for the irregular, latency-sensitive compute pattern of agent execution. Running agents on GPUs wastes 60-80% of compute capacity on idle cycles waiting for tool responses and context switches.
WHY NOW
What changed in 2025–2026
The agent paradigm shifted from research curiosity to production reality in 2025. Major companies are deploying millions of AI agents for customer service, coding, research, and operations. NVIDIA's dominance in training doesn't extend to inference — the inference market is fragmenting and open to new architectures. TSMC's advanced packaging and chiplet designs make it feasible for startups to design custom silicon without building their own fabs.
MARKET CONTEXT
The size of the opportunity
The AI inference chip market is projected to reach $70B by 2028. NVIDIA holds 80%+ of the training market but inference is far more competitive — Groq, Cerebras, and dozens of others have demonstrated that purpose-built architectures can beat GPUs on inference workloads. The agent-specific chip market is completely unserved. Every major cloud provider and enterprise deploying agents will need this hardware.
FOUNDER FIT
Who should build this
This requires world-class chip architects — founders who have designed ASICs or processor cores at companies like Apple, Google, AMD, or NVIDIA. You need deep understanding of both silicon design and the ML workloads you're optimizing for. The compiler/software stack is equally important — a chip is only as good as its toolchain. Expect $20-50M+ in funding needed to tape out and validate. Diana Hu specifically notes the compiler is as important as the chip itself.
WHAT YC SAYS
The YC partner perspective
Diana Hu frames this as two problems in one: the chip architecture and the compiler that makes it work. Purpose-built silicon for agent execution loops could deliver 10-100x better performance per watt than GPUs for agent workloads. The agent execution pattern (short bursts of compute, frequent memory access, branching logic) maps poorly to GPU architecture but maps beautifully to custom dataflow processors.
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